The invention relates generally to digital frequency synthesis, and in particular, to digital frequency synthesis wherein frequencies may be changed rapidly with high resolution and minimal phase modulation.
Synthesis is the making up of a whole by combining separate parts or elements, and frequency synthesizers produce a range of output frequencies using this principle. Early frequency synthesizers used multiple crystals and contained as many crystal oscillators as frequency decades. Due to advances in various technologies, these multi-crystal synthesizers have now been superseded by single crystal synthesizers.
Direct synthesizers add and subtract multiples and submultiples of a single crystal oscillator frequency to provide a wide range of output frequencies. One such synthesizer is a multi-loop synthesizer which works on a "divide-and-add" principle. For example, if a 1 KHz output frequency is divided by 10 using a digital counter, the result is 100 Hz frequency resolution at one tenth the 1 KHz output frequency. Using a conventional heterodyne frequency converter or "mixer", the resulting 100 Hz frequency may be added to the 1 KHz output frequency to generate successive 100 Hz steps. The 100 Hz frequency may also be divided by 10 to yield 10 Hz steps. These 10 Hz steps may then be added and/or subtracted to any of the preceding frequencies. Unfortunately, direct synthesizers suffer some serious drawbacks including generation of unwanted frequencies by the mixers requiring extensive filtering, a high sensitivity to wideband phase noise, complex circuitry, and a relatively high manufacturing cost.
The required frequency range in most current synthesizers is obtained using a variable voltage-controlled oscillator (VCO) whose output frequency is corrected by comparison with a reference frequency. This type of synthesizer is oftentimes referred to as an indirect synthesizer.
A block diagram of a known phase-locked loop (PLL) digital frequency synthesizer 10 is shown in FIG. 1. The frequency synthesizer 10 includes a reference frequency source/oscillator 12, a reference divider (divide-by-M) 14, a phase error detector 16, a loop filter 18, a voltage-controlled oscillator (VCO) 20, and a variable VCO divider (divide-by-N) 22. The VCO divider 22 may comprise a digital counter that generates a series of count pulses. A VCO output signal at an output frequency F.sub.vco is generated by the VCO 20 and is detected by the VCO divider 22. As those skilled in the art will readily comprehend, the output frequency F.sub.vco is used herein to designate a frequency which is typically changing in a predetermined manner. Thus, the output frequency F.sub.vco may represent one or more distinct, desired frequencies or may represent a range of desired frequencies. The VCO divider 22 counts the number of cycles of the VCO output signal and produces an output pulse after every N cycles, where N is a programmable divisor that can be varied between different count cycles. The VCO divider 22 therefore produces output pulses at a frequency of the output frequency F.sub.vco divided by the divisor N.
In order to synthesize multiple different frequencies from the VCO 20, the VCO divider 22 is programmed to divide by different output divisors N whose value is variably set by a control mechanism 23 based on a desired value for the output frequency F.sub.vco. In a typical application, the desired value of the output frequency F.sub.vco may be one of many possible radio frequency (RF) channels for RF transmission or RF reception. Of course, if the variable output divisor N is equal to 1, the VCO divider 22 would output count pulses forming an output pulse train having a frequency substantially identical to the current value of the output frequency F.sub.vco.
The output pulse train generated by the VCO divider 22 is fed back to the phase error detector 16 for comparison with a reference frequency F.sub.ref. The reference frequency F.sub.ref is usually a fixed, accurate frequency generated by a crystal oscillator; but in some cases, it is a variable frequency derived from some other source that may include another frequency synthesizer. Since the reference frequency source 12 generates a reference frequency F.sub.ref that is usually higher than the desired step size between frequencies generated by the VCO 20, the reference frequency F.sub.ref is transformed by the reference divider 14 into a reference pulse train having a frequency corresponding to the desired step size. The reference divider 14 divides the reference frequency F.sub.ref by a reference integer M. The reference integer M is selected so that the phase detector 16 is able to compare the reference pulse train and the output pulse train generated by the VCO divider 22.
The difference/error in phase or frequency between the compared pulse trains is output as a phase error signal (typically a voltage) by the phase detector 16. The phase error signal is filtered by the loop filter 18 to produce an output error, or control, signal. The loop filter 18 is typically a low-pass filter. The characteristics of the loop filter 18 govern how the PLL responds to changes in the phase error signal. The VCO 20 is a sinusoidal oscillator whose frequency is controlled by the output error signal. A negative value for the output error signal causes the VCO 20 to decrease the output frequency F.sub.vco and a positive value for the output error signal causes the VCO 20 to increase the output frequency F.sub.vco.
In this way, the VCO 20 may be tuned through a wide range of desired values for the output frequency F.sub.vco simply by varying the output error signal. By continuously comparing the output frequency F.sub.vco of the VCO 20 with a reference frequency F.sub.ref having a desired accuracy and, in response thereto, continuously correcting the output error signal, the frequency synthesizer 10 can achieve a very high accuracy. Indeed, the accuracy of the frequency synthesizer 10 can be on the order of one part per million or better, which is typically the accuracy of the reference frequency source 12.
As mentioned above, the reference frequency F.sub.ref generated by the reference frequency source 12 is usually not equal to the output frequency F.sub.vco to which the VCO 20 is currently tuned; otherwise, the reference frequency source 12 could be used directly to generate the output frequency F.sub.vco. Because the reference frequency F.sub.ref and the desired value of the output frequency F.sub.vco typically differ, they must first be reduced by division to some common submultiple frequency before they can be compared. For example, suppose a desired range of the output frequency F.sub.vco includes a series of frequencies spaced apart by frequency steps of 25 KHz, for example, 1000.000 MHz, 1000.025 MHz, 1000.050 MHz . . . , and the reference frequency F.sub.ref is 12.8 MHz. The reference frequency F.sub.ref would need to be divided by 512 (the reference integer M equal to 512) by the reference divider 14 to generate a reference pulse train having a frequency of 25 KHz which is the spacing between the desired series of output frequencies F.sub.vco. For this example, the reference divider 14 may be comprised of a 9-stage binary counter (2.sup.9 =512) to produce such a reference pulse train.
The output frequency F.sub.vco of the VCO 20 is divided by the variable output divisor N in the VCO divider 22. The variable output divisor N is set to one of the numbers in the series 40000, 40001, 40002 . . . corresponding to the desired output frequency F.sub.vco expressed in multiples of 25 KHz, i.e., 1000.000 MHz/40000=25 KHz, 1000.025 MHz/40001=25 KHz, 1000.050 MHz/40002=25 KHz . . . If the output frequency F.sub.vco is at the desired value, the VCO divider 22 will generate pulses at the same 25 KHz rate as the reference divider 14. Any difference between the frequencies of the reference pulse train and the output pulse train is detected by the phase detector 16 which generates an appropriate phase error signal, or voltage, to correct the output frequency F.sub.vco.
In many frequency synthesizer applications, relatively small frequency steps, or fine resolution, in the output frequency F.sub.vco is desired. The minimum frequency steps, or resolution, between different values of the output frequency F.sub.vco is a function of the value of the reference integer M and the reference frequency F.sub.ref. Consequently, the reference frequency F.sub.ref should be minimized and the reference integer M should be large. Unfortunately, as those skilled in the art will readily comprehend, lowering the reference frequency F.sub.ref tends to cause the loop to become unstable unless the loop bandwidth is correspondingly narrowed. In particular, loop bandwidth should preferably be an order of magnitude lower than the reference frequency F.sub.ref to assure that the loop filter 18 adequately smoothes the phase error signal generated by the phase detector 16. At frequencies within the loop bandwidth, phase jitter, or phase noise, caused by a sudden phase change tends to be corrected by negative feedback in the PLL. Unfortunately, at frequencies outside the loop bandwidth, phase jitter is not corrected and the PLL may become noisy or unstable. A further disadvantage of a PLL with a narrow loop bandwidth is relatively lengthy settling times before the output frequency F.sub.vco reaches its desired value. Therefore, in designing a frequency synthesizer the need for fine resolution which requires a narrow loop bandwidth must be balanced with the need for low phase jitter, and the corresponding PLL stability, which requires a wide loop bandwidth. This incompatibility between fine resolution of the output frequency F.sub.vco and PLL stability is a significant disadvantage of simple single loop synthesizers.
Returning to the frequency synthesizer 10 of FIG. 1, the frequency of the pulses (in the reference pulse train and the output pulse train) received by the phase error detector 16 is dependent upon the spacing between frequencies in the desired series of output frequencies. This spacing between frequencies is known as "channel spacing" or "frequency resolution". When narrower channel spacing or finer frequency resolution is desired, the pulses received by the phase error detector 16 become proportionally less frequent.
For a channel spacing of 100 Hz, pulses from the VCO divider 22 and the reference divider 14 are received at a rate of one pulse per 10 milliseconds (1/100 Hz=10 msec). If a smaller channel spacing is desired, for example 1 Hz, the phase detector 16 only receives one pulse per second (1/1 Hz=1 s). Consequently, the phase detector 16 has only one opportunity per second to measure the phase error between the output pulse train (derived from the current value of the output frequency F.sub.vco) and the reference pulse train. Because of this relatively long time between phase error measurements, narrow channel spacing may result in an undesirable delay before the frequency synthesizer 10 selects and settles down to a new output frequency with the desired precision. Therefore, there is yet another frequency synthesizer design tradeoff--resolution and speed. Finer frequency resolution also reduces the synthesizer's ability to correct for undesired short-term fluctuations in the output frequency F.sub.vco which can arise, for example, from mechanical vibrations.
Frequency changing speed may be decoupled from frequency resolution by varying an output divisor N used to reduce a particular output frequency for comparison to a reference frequency. Such a synthesizer using a variable output divisor is referred to hereafter as a "fractional-N" synthesizer since it synthesizes frequencies by apparently dividing by values of the output divisor N which are not whole numbers. As will be apparent, the output divisor N is variable around some base value, for example, the output divisor N can be varied between N and N+1 or N and N-1.
In operation, a fractional synthesizer varies the output divisor N between two or more integers, such as N and N+1, in a predetermined divisor sequence to approximate division with a non-integral output divisor. The fractional synthesizer may also compensate for any resulting post-division, fractional remainders. For example, suppose that in a certain fractional-N synthesizer design the output divisor N should optimally be equal to N+(1/3). As was stated, conventional non-fractional-N synthesizers only divide the output frequency F.sub.vco by integers. However, dividing by the output divisor N equal to N+(1/3) may be approximated by dividing by the integer sequence: EQU N=N, N, N+1, N, N, N+1, N, N, N+1
Accordingly, if the output frequency F.sub.vco is divided by the output integer N two times out of three and by the output integer N plus 1 one time out of three, the output frequency F.sub.vco will be divided, on average, by the output digital divisor N having a value of N+1/3. This type of fractional-N synthesizer, as described below, results in a periodic approximation error which is large and must be accurately compensated.
The approximation of a fractional part by varying the output divider N between N and N+1 according to some pattern gives rise to a periodic error in the oscillator control voltage which is termed "fractional ripple". In prior art fractional-N synthesizers, the periodic error is of such magnitude that steps must be taken to reduce it. A block diagram of a known technique described in U.S. Pat. No. 4,179,670 issued to Kingsbury for reducing the error is shown in FIG. 1B. Typically, this prior art technique equates the instantaneous digital value in the fractional-N accumulator 38 with the approximation error, and converts the digital value to an analog compensation signal using the D/A converter 40. The compensation signal must further be scaled down in proportion to the N value of the divider 22 before being subtracted from the phase comparator output at the ripple compensator 32. The Kingsbury patent discloses that the variable divider 22 has an output pulse mark space ratio proportional to 1/N and thus the desired scaling down by the factor N can be achieved by chopping the compensation signal from the D/A convertor 40 using a chopper switch 41 driven by the output pulses from the variable divider 22.
Despite these ingenuities of the prior art, fractional-N ripple compensation remains prone to analog circuit component tolerances, and thus a need exists to reduce the amount of ripple to be compensated or to otherwise devise simpler methods of compensation, which improvements may be obtained by practicing the present invention as described herein.